In accordance with miniaturization of a semiconductor fabrication technology, a current which is referred to as a leakage current flowing in a transistor which is turned OFF is increased, and a problem is posed by an increase in power owing to a leakage current of a circuit which is not operated. As a technology of suppressing the leakage current, there has been used a power source interrupting technology of reducing a leakage current by interrupting a power source when a circuit is not operated.
FIG. 34A and FIG. 34B show an outline of a power source interrupting technology. In a state ACTIVE in which a circuit is operated, the circuit LOGIC1 is normally operated by applying a potential the same as a power source voltage VDD to a local power source VDCL which is a power source of the circuit LOGIC1. In a standby state STAND-BY in which the circuit is not operated, by setting high a potential of a control line CSW of a power source switch. SW which is inserted between the power source VDCL of the circuit and a power source line VDD, the power source switch is interrupted. Thereby, a potential of the local power source VDCL is lowered, and a leakage current Ileak flowing in the circuit LOGIC1 can be reduced. In a case where the standby state recovers to an operating state, when the power source switch SW is abruptly turned ON, a large current for charging the local power source flows abruptly, thereby, a large power source noise is generated at the power source VDD, and there is a possibility that a circuit of a portion at which the power source is not interrupted causes an erroneous operation.
Therefore, in order to resolve the problem, there has been a technology of suppressing generation of a power source noise by setting a potential of a control line of a power source switch to an intermediate potential for a constant period of time in recovering from power source interruption, making a change in a potential of a local power source during a time period of shifting from a standby state to an operating state gradual, and restraining a current I (SW) flowing in a power source switch SW to be small during the time period as described in FIG. 5 of Japanese Unexamined Patent Publication No. 2008-34667(JP-A-2008-34667).